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Cover of RTL modeling with SystemVerilog for simulation and synthesis using SystemVerilog for ASIC and FPGA design

RTL modeling with SystemVerilog for simulation and synthesis using SystemVerilog for ASIC and FPGA design

by Stuart Sutherland

Verilog (Computer hardware description language)Electronic digital computers -- Design and constructionComputer simulation

xxxi, 453 pages : 23 cm

Writing a summary for young readers…

For young readers

Book data: Open Library